binaryDiv
/
eepyPad
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
eepyPad/README.md

2.8 KiB
Raw Blame History

The eepyPad

Custom macro key pad with mechanical low-profile (Choc) switches.

Repository structure

How-to

Generating the PCB

To generate the KiCad PCB file with Ergogen, first install Ergogen using npm: npm install.

Then, run npm run ergogen. You can find the KiCad file in ergogen/output/pcbs/eepypad.kicad_pcb. Copy the file to kicad/eepypad.kicad_pcb.

Open the file in KiCad (create a project if non exists yet). Finalize the PCB in KiCad.

  1. (Optional) Run the Design Rules Checker. Check the errors. Most of them can be ignored/excluded.
    • All "Footprint not found in libraries" can be ignored completely. This is due to how Ergogen generates the PCB.
    • The "Board edge clearance" violations are mostly about the cutout for the LED chips.
  2. Add VCC and GND planes.
    • Menu: File -> Board Setup
    • On "Physical Stackup", change the copper layer number to 4.
    • On "Board Editor Layers", change the type of In1.Cu and In2.Cu to "power plane".
    • NOTE: In1.Cu will be the VCC plane, In2.Cu will be a GND plane.
  3. Add filled zones to the VCC and GND planes.
    • Select the In1.Cu layer.
    • Use the "Add a filled zone" tool and draw a rectangle that contains the entire board. Assign the zone to VCC.
    • Repeat the same process for the In2.Cu layer and assign the zone to GND.
    • The zones don't need to be filled just yet.
  4. Add another filled zone on the B.Cu layer and assign it to GND.
  5. Route all signal traces (no VCC or GND yet). Recommended order:
    • Matrix rows (on B.Cu)
    • Matrix columns (with vias on F.Cu)
    • NeoPixel data pins
    • Connect everything to the MCU.
  6. Route VCC traces.
    • Connect the VCC traces between the NeoPixel chips and the capacitors with a 0.750 mm track.
    • Place free-standing vias (Ctrl+Shift+V) in the middle of the just created VCC traces.
  7. Route GND traces.
    • Draw short GND traces with a 0.750 mm track and a via at the end next to the GND pads of the NeoPixel chips.
  8. Fill all zones by pressing B. Make sure that all nets are routed.
  9. Run the Design Rules Checker and make sure there are no (relevant) violations.
  10. Add some fancy text on the F.Silkscreen layer.

TODO: How to export?

Used software

Resources