Add KiCad PCB file
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F8D4956E224DA232
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@ -22,3 +22,15 @@ dist
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# Ergogen
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/ergogen/output
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# Kicad temporary files
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kicad/*-backups/
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*.bak
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*.kicad_pcb-bak
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*.kicad_sch-bak
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*.kicad_prl
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*-save.pro
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*-save.kicad_pcb
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~*.lck
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_autosave-*
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fp-info-cache
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41
README.md
41
README.md
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@ -7,6 +7,47 @@ Custom macro key pad with mechanical low-profile (Choc) switches.
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- `/layouts`: Keyboard layouts created with the [Keyboard Layout Editor](http://www.keyboard-layout-editor.com)
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- `/ergogen`: [Ergogen](https://docs.ergogen.xyz/) files to generate outlines, cases and PCBs
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## How-to
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### Generating the PCB
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To generate the KiCad PCB file with Ergogen, first install Ergogen using npm: `npm install`.
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Then, run `npm run ergogen`. You can find the KiCad file in `ergogen/output/pcbs/eepypad.kicad_pcb`.
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Copy the file to `kicad/eepypad.kicad_pcb`.
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Open the file in KiCad (create a project if non exists yet). Finalize the PCB in KiCad.
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1. (Optional) Run the Design Rules Checker. Check the errors. Most of them can be ignored/excluded.
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- All "Footprint not found in libraries" can be ignored completely. This is due to how Ergogen generates the PCB.
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- The "Board edge clearance" violations are mostly about the cutout for the LED chips.
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2. Add VCC and GND planes.
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- Menu: `File -> Board Setup`
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- On "Physical Stackup", change the copper layer number to 4.
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- On "Board Editor Layers", change the type of `In1.Cu` and `In2.Cu` to "power plane".
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- NOTE: `In1.Cu` will be the VCC plane, `In2.Cu` will be a GND plane.
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3. Add filled zones to the VCC and GND planes.
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- Select the `In1.Cu` layer.
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- Use the "Add a filled zone" tool and draw a rectangle that contains the entire board. Assign the zone to VCC.
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- Repeat the same process for the `In2.Cu` layer and assign the zone to GND.
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- The zones don't need to be filled just yet.
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4. Add another filled zone on the `B.Cu` layer and assign it to GND.
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5. Route all signal traces (no VCC or GND yet). Recommended order:
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- Matrix rows (on `B.Cu`)
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- Matrix columns (with vias on `F.Cu`)
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- NeoPixel data pins
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- Connect everything to the MCU.
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6. Route VCC traces.
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- Connect the VCC traces between the NeoPixel chips and the capacitors with a 0.750 mm track.
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- Place free-standing vias (Ctrl+Shift+V) in the middle of the just created VCC traces.
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7. Route GND traces.
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- Draw short GND traces with a 0.750 mm track and a via at the end next to the GND pads of the NeoPixel chips.
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8. Fill all zones by pressing B. Make sure that all nets are routed.
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9. Run the Design Rules Checker and make sure there are no (relevant) violations.
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10. Add some fancy text on the `F.Silkscreen` layer.
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TODO: How to export?
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## Used software
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- [Keyboard Layout Editor](http://www.keyboard-layout-editor.com)
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,533 @@
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{
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"board": {
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"3dviewports": [],
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.049999999999999996,
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"copper_line_width": 0.19999999999999998,
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"copper_text_italic": false,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"copper_text_upright": false,
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"courtyard_line_width": 0.049999999999999996,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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"extension_offset": 500000,
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"keep_text_aligned": true,
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"suppress_zeroes": false,
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"text_position": 0,
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"units_format": 1
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},
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"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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"fab_text_size_h": 1.0,
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.09999999999999999,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 0.762,
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"height": 1.524,
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"width": 1.524
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},
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"silk_line_width": 0.12,
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"silk_text_italic": false,
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"silk_text_size_h": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_thickness": 0.15,
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"silk_text_upright": false,
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"zones": {
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"min_clearance": 0.508
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}
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},
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"diff_pair_dimensions": [
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{
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"gap": 0.0,
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"via_gap": 0.0,
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"width": 0.0
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}
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],
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"drc_exclusions": [],
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"meta": {
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"filename": "board_design_settings.json",
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"connection_width": "warning",
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"copper_edge_clearance": "error",
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"copper_sliver": "warning",
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"courtyards_overlap": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint": "error",
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"footprint_type_mismatch": "ignore",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"isolated_copper": "warning",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"lib_footprint_issues": "ignore",
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"lib_footprint_mismatch": "warning",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "warning",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_edge_clearance": "warning",
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"silk_over_copper": "ignore",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"solder_mask_bridge": "error",
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"starved_thermal": "error",
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"text_height": "warning",
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"text_thickness": "warning",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zones_intersect": "error"
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},
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"rules": {
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_connection": 0.0,
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"min_copper_edge_clearance": 0.075,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_drill": 0.09999999999999999,
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"min_resolved_spokes": 2,
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"min_silk_clearance": 0.0,
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"min_text_height": 0.7999999999999999,
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"min_text_thickness": 0.08,
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"min_through_hole_diameter": 0.3,
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"min_track_width": 0.19999999999999998,
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"min_via_annular_width": 0.09999999999999999,
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"min_via_diameter": 0.39999999999999997,
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"solder_mask_to_copper_clearance": 0.0,
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"use_height_for_length_calcs": true
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},
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"teardrop_options": [
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{
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"td_allow_use_two_tracks": true,
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"td_curve_segcount": 5,
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"td_on_pad_in_zone": false,
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"td_onpadsmd": true,
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"td_onroundshapesonly": false,
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"td_ontrackend": false,
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"td_onviapad": true
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}
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],
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"teardrop_parameters": [
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{
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"td_curve_segcount": 0,
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"td_height_ratio": 1.0,
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"td_length_ratio": 0.5,
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"td_maxheight": 2.0,
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"td_maxlen": 1.0,
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"td_target_name": "td_round_shape",
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"td_width_to_size_filter_ratio": 0.9
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},
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{
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"td_curve_segcount": 0,
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"td_height_ratio": 1.0,
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"td_length_ratio": 0.5,
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"td_maxheight": 2.0,
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"td_maxlen": 1.0,
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"td_target_name": "td_rect_shape",
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"td_width_to_size_filter_ratio": 0.9
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},
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{
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"td_curve_segcount": 0,
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"td_height_ratio": 1.0,
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"td_length_ratio": 0.5,
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"td_maxheight": 2.0,
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"td_maxlen": 1.0,
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"td_target_name": "td_track_end",
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"td_width_to_size_filter_ratio": 0.9
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}
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],
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"track_widths": [
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0.0,
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0.75
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],
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"via_dimensions": [
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{
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"diameter": 0.0,
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"drill": 0.0
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}
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],
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"zones_allow_external_fillets": false
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},
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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},
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"libraries": {
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"pinned_footprint_libs": [],
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"pinned_symbol_libs": []
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},
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"meta": {
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"filename": "eepypad.kicad_pro",
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"version": 1
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},
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"net_settings": {
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"classes": [
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{
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6
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}
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],
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"meta": {
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"version": 3
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},
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"net_colors": null,
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"netclass_assignments": null,
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"netclass_patterns": [
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{
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"netclass": "Default",
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"pattern": ""
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},
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{
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"netclass": "Default",
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"pattern": "one_one"
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},
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{
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"netclass": "Default",
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"pattern": "P5"
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},
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{
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"netclass": "Default",
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"pattern": "one_two"
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},
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{
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"netclass": "Default",
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"pattern": "P6"
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},
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{
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"netclass": "Default",
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"pattern": "one_three"
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},
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{
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"netclass": "Default",
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"pattern": "P7"
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},
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{
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"netclass": "Default",
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"pattern": "one_four"
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},
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{
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"netclass": "Default",
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"pattern": "P8"
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},
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{
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"netclass": "Default",
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"pattern": "one_five"
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},
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{
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"netclass": "Default",
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"pattern": "P9"
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||||
},
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{
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"netclass": "Default",
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"pattern": "two_one"
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},
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{
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"netclass": "Default",
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"pattern": "two_two"
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},
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{
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"netclass": "Default",
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"pattern": "two_three"
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},
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{
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"netclass": "Default",
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"pattern": "two_four"
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},
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{
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"netclass": "Default",
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"pattern": "two_five"
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},
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{
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"netclass": "Default",
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"pattern": "three_one"
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},
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{
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"netclass": "Default",
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"pattern": "three_two"
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||||
},
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{
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"netclass": "Default",
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"pattern": "three_three"
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},
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{
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"netclass": "Default",
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"pattern": "three_four"
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||||
},
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{
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||||
"netclass": "Default",
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||||
"pattern": "three_five"
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||||
},
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{
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"netclass": "Default",
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||||
"pattern": "four_one"
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||||
},
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||||
{
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||||
"netclass": "Default",
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||||
"pattern": "four_two"
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||||
},
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||||
{
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||||
"netclass": "Default",
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||||
"pattern": "four_three"
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||||
},
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||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "four_four"
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||||
},
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||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "four_five"
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||||
},
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||||
{
|
||||
"netclass": "Default",
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||||
"pattern": "five_one"
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||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "five_two"
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||||
},
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||||
{
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||||
"netclass": "Default",
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||||
"pattern": "five_three"
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||||
},
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||||
{
|
||||
"netclass": "Default",
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||||
"pattern": "five_four"
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||||
},
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||||
{
|
||||
"netclass": "Default",
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||||
"pattern": "five_five"
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||||
},
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||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "P3"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "P4"
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||||
},
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||||
{
|
||||
"netclass": "Default",
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||||
"pattern": "GND"
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||||
},
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||||
{
|
||||
"netclass": "Default",
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||||
"pattern": "P18"
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||||
},
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||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "P15"
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||||
},
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||||
{
|
||||
"netclass": "Default",
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||||
"pattern": "P14"
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||||
},
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||||
{
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||||
"netclass": "Default",
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||||
"pattern": "P16"
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||||
},
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||||
{
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||||
"netclass": "Default",
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||||
"pattern": "P10"
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||||
},
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||||
{
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||||
"netclass": "Default",
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||||
"pattern": "led_dout_two_one"
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||||
},
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||||
{
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||||
"netclass": "Default",
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||||
"pattern": "led_dout_one_one"
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||||
},
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||||
{
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||||
"netclass": "Default",
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||||
"pattern": "VCC"
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||||
},
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||||
{
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||||
"netclass": "Default",
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||||
"pattern": "led_dout_two_three"
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||||
},
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||||
{
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||||
"netclass": "Default",
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||||
"pattern": "led_dout_one_three"
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||||
},
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||||
{
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||||
"netclass": "Default",
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||||
"pattern": "led_dout_two_five"
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||||
},
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||||
{
|
||||
"netclass": "Default",
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||||
"pattern": "led_dout_one_five"
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||||
},
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||||
{
|
||||
"netclass": "Default",
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||||
"pattern": "led_dout_three_one"
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||||
},
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||||
{
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||||
"netclass": "Default",
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||||
"pattern": "led_dout_three_three"
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||||
},
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||||
{
|
||||
"netclass": "Default",
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||||
"pattern": "led_dout_three_five"
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||||
},
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||||
{
|
||||
"netclass": "Default",
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||||
"pattern": "led_dout_four_one"
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||||
},
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||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_four_three"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_four_five"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_five_one"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_five_three"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "P19"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_five_two"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_five_four"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_one_two"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_one_four"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_two_two"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_two_four"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_three_two"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_three_four"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_four_two"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "led_dout_four_four"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "RAW"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "RST"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "P21"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "P20"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "P1"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "P0"
|
||||
},
|
||||
{
|
||||
"netclass": "Default",
|
||||
"pattern": "P2"
|
||||
}
|
||||
]
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": []
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
}
|
||||
Loading…
Reference in New Issue