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Add routed KiCad PCB file

This commit is contained in:
Lexi / Zoe 2024-06-13 00:13:22 +02:00
parent 2b0a7f077c
commit f2101a3402
Signed by: binaryDiv
GPG Key ID: F8D4956E224DA232
3 changed files with 39193 additions and 25 deletions
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28
README.md
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@ -34,31 +34,9 @@ Open the file in KiCad (create a project if non exists yet). Finalize the PCB in
1. (Optional) Run the Design Rules Checker. Check the errors. Most of them can be ignored/excluded.
- All "Footprint not found in libraries" can be ignored completely. This is due to how Ergogen generates the PCB.
- The "Board edge clearance" violations are mostly about the cutout for the LED chips.
2. Add VCC and GND planes.
- Menu: `File -> Board Setup`
- On "Physical Stackup", change the copper layer number to 4.
- On "Board Editor Layers", change the type of `In1.Cu` and `In2.Cu` to "power plane".
- NOTE: `In1.Cu` will be the VCC plane, `In2.Cu` will be a GND plane.
3. Add filled zones to the VCC and GND planes.
- Select the `In1.Cu` layer.
- Use the "Add a filled zone" tool and draw a rectangle that contains the entire board. Assign the zone to VCC.
- Repeat the same process for the `In2.Cu` layer and assign the zone to GND.
- The zones don't need to be filled just yet.
4. Add another filled zone on the `B.Cu` layer and assign it to GND.
5. Route all signal traces (no VCC or GND yet). Recommended order:
- Matrix rows (on `B.Cu`)
- Matrix columns (with vias on `F.Cu`)
- NeoPixel data pins
- Connect everything to the MCU.
6. Route VCC traces.
- Connect the VCC traces between the NeoPixel chips and the capacitors with a 0.750 mm track.
- Place free-standing vias (Ctrl+Shift+V) in the middle of the just created VCC traces.
7. Route GND traces.
- Draw short GND traces with a 0.750 mm track and a via at the end next to the GND pads of the NeoPixel chips.
8. Fill all zones by pressing B. Make sure that all nets are routed.
9. Run the Design Rules Checker and make sure there are no (relevant) violations.
10. Add some fancy text on the `F.Silkscreen` layer.
2. Route all signal traces.
3. Run the Design Rules Checker and make sure there are no (relevant) violations.
4. Add some fancy text on the `F.Silkscreen` layer.
#### Export Gerber files

38743
kicad/protoeepyboard.kicad_pcb Normal file
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447
kicad/protoeepyboard.kicad_pro Normal file
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@ -0,0 +1,447 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.05,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.1,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.12,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "ignore",
"hole_near_hole": "error",
"holes_co_located": "ignore",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "ignore",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "ignore",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.075,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.2,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.4,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 1.0
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [],
"zones_allow_external_fillets": false
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "protoeepyboard.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "Default",
"pattern": ""
},
{
"netclass": "Default",
"pattern": "P10"
},
{
"netclass": "Default",
"pattern": "outer_mod"
},
{
"netclass": "Default",
"pattern": "outer_bottom"
},
{
"netclass": "Default",
"pattern": "outer_home"
},
{
"netclass": "Default",
"pattern": "outer_top"
},
{
"netclass": "Default",
"pattern": "outer_num"
},
{
"netclass": "Default",
"pattern": "P8"
},
{
"netclass": "Default",
"pattern": "one_mod"
},
{
"netclass": "Default",
"pattern": "one_bottom"
},
{
"netclass": "Default",
"pattern": "one_home"
},
{
"netclass": "Default",
"pattern": "one_top"
},
{
"netclass": "Default",
"pattern": "one_num"
},
{
"netclass": "Default",
"pattern": "P6"
},
{
"netclass": "Default",
"pattern": "two_bottom"
},
{
"netclass": "Default",
"pattern": "two_home"
},
{
"netclass": "Default",
"pattern": "two_top"
},
{
"netclass": "Default",
"pattern": "two_num"
},
{
"netclass": "Default",
"pattern": "P4"
},
{
"netclass": "Default",
"pattern": "three_bottom"
},
{
"netclass": "Default",
"pattern": "three_home"
},
{
"netclass": "Default",
"pattern": "three_top"
},
{
"netclass": "Default",
"pattern": "three_num"
},
{
"netclass": "Default",
"pattern": "P2"
},
{
"netclass": "Default",
"pattern": "four_bottom"
},
{
"netclass": "Default",
"pattern": "four_home"
},
{
"netclass": "Default",
"pattern": "four_top"
},
{
"netclass": "Default",
"pattern": "four_num"
},
{
"netclass": "Default",
"pattern": "P12"
},
{
"netclass": "Default",
"pattern": "five_bottom"
},
{
"netclass": "Default",
"pattern": "five_home"
},
{
"netclass": "Default",
"pattern": "five_top"
},
{
"netclass": "Default",
"pattern": "five_num"
},
{
"netclass": "Default",
"pattern": "one_default"
},
{
"netclass": "Default",
"pattern": "two_default"
},
{
"netclass": "Default",
"pattern": "three_default"
},
{
"netclass": "Default",
"pattern": "four_default"
},
{
"netclass": "Default",
"pattern": "P9"
},
{
"netclass": "Default",
"pattern": "P7"
},
{
"netclass": "Default",
"pattern": "P5"
},
{
"netclass": "Default",
"pattern": "P3"
},
{
"netclass": "Default",
"pattern": "P1"
},
{
"netclass": "Default",
"pattern": "P11"
}
]
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"legacy_lib_dir": "",
"legacy_lib_list": []
},
"sheets": [],
"text_variables": {}
}