Ergogen: Fix DRC issues in KiCad footprints
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parent
671f85b13e
commit
f438b19352
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@ -8,6 +8,7 @@ module.exports = {
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body: p => `
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(module C_0805_2012Metric (layer ${p.side}.Cu) (tedit 5F68FEEE)
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${p.at /* parametric position */}
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(attr smd)
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${'' /* footprint reference */}
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(fp_text reference "${p.ref}" (at 0 0) (layer ${p.side}.SilkS) ${p.ref_hide} (effects (font (size 1.27 1.27) (thickness 0.15))))
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@ -28,6 +28,7 @@ module.exports = {
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const standard = `
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(module PG1350 (layer F.Cu) (tedit 5DD50112)
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${p.at /* parametric position */}
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(attr smd)
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${'' /* footprint reference */}
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(fp_text reference "${p.ref}" (at 0 0) (layer F.SilkS) ${p.ref_hide} (effects (font (size 1.27 1.27) (thickness 0.15))))
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@ -61,7 +62,8 @@ module.exports = {
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return `
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${'' /* switch marks */}
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(fp_line (start -7 -7) (end 7 -7) (layer ${def_side}.SilkS) (width 0.15))
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(fp_line (start -7 -7) (end -1.5 -7) (layer ${def_side}.SilkS) (width 0.15))
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(fp_line (start 1.5 -7) (end 7 -7) (layer ${def_side}.SilkS) (width 0.15))
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(fp_line (start 7 -7) (end 7 7) (layer ${def_side}.SilkS) (width 0.15))
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(fp_line (start 7 7) (end -7 7) (layer ${def_side}.SilkS) (width 0.15))
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(fp_line (start -7 7) (end -7 -7) (layer ${def_side}.SilkS) (width 0.15))
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@ -8,6 +8,7 @@ module.exports = {
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body: p => `
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(module SmdDiode (layer ${p.side}.Cu) (tedit 65D012FE)
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${p.at /* parametric position */}
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(attr smd)
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${'' /* footprint reference */}
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(fp_text reference "${p.ref}" (at 0 0) (layer ${p.side}.SilkS) ${p.ref_hide} (effects (font (size 1.27 1.27) (thickness 0.15))))
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@ -107,7 +107,7 @@ module.exports = {
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for (let i = 0; i < PINS_PER_SIDE; i++) {
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pin_pad_body += `
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(pad ${i + offset} thru_hole circle (at ${sign}8.89 ${pin_pos_y(i)} 0)
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(size 1.7526 1.7526) (drill 1.0922) (layers *.Cu *.SilkS *.Mask) ${p[pin_names[i]]}
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(size 1.7526 1.7526) (drill 1.0922) (layers *.Cu *.Mask) ${p[pin_names[i]]}
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)`;
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}
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return pin_pad_body;
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@ -13,6 +13,7 @@ module.exports = {
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body: p => `
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(module SK6812-MINI-E (layer F.Cu) (tedit 53BEE615)
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${p.at /* parametric position */}
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(attr smd)
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${'' /* footprint reference */}
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(fp_text reference "${p.ref}" (at 0 0) (layer ${p.side}.SilkS) ${p.ref_hide}
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@ -30,19 +31,19 @@ module.exports = {
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(fp_line (start -1.7 1.5) (end -1.7 -1.5) (layer Edge.Cuts) (width 0.12))
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(fp_line (start -1.7 -1.5) (end 1.7 -1.5) (layer Edge.Cuts) (width 0.12))
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(pad "1" smd rect (at -2.55 -0.75 ${p.r}) (size 1.7 0.82)
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(pad "1" smd rect (at -2.6 -0.75 ${p.r}) (size 1.6 0.82)
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(layers "${p.side}.Cu" "${p.side}.Paste" "${p.side}.Mask")
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${p.VCC}
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)
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(pad "2" smd rect (at -2.55 0.75 ${p.r}) (size 1.7 0.82)
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(pad "2" smd rect (at -2.6 0.75 ${p.r}) (size 1.6 0.82)
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(layers "${p.side}.Cu" "${p.side}.Paste" "${p.side}.Mask")
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${p.dout}
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)
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(pad "4" smd rect (at 2.55 -0.75 ${p.r}) (size 1.7 0.82)
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(pad "4" smd rect (at 2.6 -0.75 ${p.r}) (size 1.6 0.82)
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(layers "${p.side}.Cu" "${p.side}.Paste" "${p.side}.Mask")
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${p.din}
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)
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(pad "3" smd roundrect (at 2.55 0.75 ${p.r}) (size 1.7 0.82)
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(pad "3" smd roundrect (at 2.6 0.75 ${p.r}) (size 1.6 0.82)
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(layers "${p.side}.Cu" "${p.side}.Paste" "${p.side}.Mask")
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(roundrect_rratio 0.25)
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${p.GND}
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